1. Technical Field
Various embodiments generally relate to semiconductor systems, and more particularly, semiconductor systems including an efficient measurement scheme of a setup time and a hold time.
2. Related Art
Synchronous dynamic random access memory (SDRAM) devices may receive or output data using an internal clock signal. The internal clock signal is synchronized with an external clock signal. Accordingly, the SDRAM devices may operate at a high speed because the data is transmitted in response to the internal clock signal.
In the SDRAM devices, it may be important to guarantee a setup time and a hold time of data with respect to the internal clock signal. In this way, data may be normally read out or written to the SDRAM device. In certain situations, the data should be applied to input pins of the SDRAM devices earlier than a switching moment of the external clock signal by at least the setup time. Also, the data should be maintained for at least the hold time starting from the switching moment of the external clock signal. That is, the setup time equates to a time corresponding to a front portion of a data valid window, and the hold time equates to a time corresponding to a rear portion of the data valid window.